6 research outputs found
Demonstrating Analog Inference on the BrainScaleS-2 Mobile System
We present the BrainScaleS-2 mobile system as a compact analog inference
engine based on the BrainScaleS-2 ASIC and demonstrate its capabilities at
classifying a medical electrocardiogram dataset. The analog network core of the
ASIC is utilized to perform the multiply-accumulate operations of a
convolutional deep neural network. At a system power consumption of 5.6W, we
measure a total energy consumption of 192uJ for the ASIC and achieve a
classification time of 276us per electrocardiographic patient sample. Patients
with atrial fibrillation are correctly identified with a detection rate of
(93.70.7)% at (14.01.0)% false positives. The system is directly
applicable to edge inference applications due to its small size, power
envelope, and flexible I/O capabilities. It has enabled the BrainScaleS-2 ASIC
to be operated reliably outside a specialized lab setting. In future
applications, the system allows for a combination of conventional machine
learning layers with online learning in spiking neural networks on a single
neuromorphic platform
Inference with Artificial Neural Networks on Analog Neuromorphic Hardware
The neuromorphic BrainScaleS-2 ASIC comprises mixed-signal neurons and
synapse circuits as well as two versatile digital microprocessors. Primarily
designed to emulate spiking neural networks, the system can also operate in a
vector-matrix multiplication and accumulation mode for artificial neural
networks. Analog multiplication is carried out in the synapse circuits, while
the results are accumulated on the neurons' membrane capacitors. Designed as an
analog, in-memory computing device, it promises high energy efficiency.
Fixed-pattern noise and trial-to-trial variations, however, require the
implemented networks to cope with a certain level of perturbations. Further
limitations are imposed by the digital resolution of the input values (5 bit),
matrix weights (6 bit) and resulting neuron activations (8 bit). In this paper,
we discuss BrainScaleS-2 as an analog inference accelerator and present
calibration as well as optimization strategies, highlighting the advantages of
training with hardware in the loop. Among other benchmarks, we classify the
MNIST handwritten digits dataset using a two-dimensional convolution and two
dense layers. We reach 98.0% test accuracy, closely matching the performance of
the same network evaluated in software
Accelerated physical emulation of Bayesian inference in spiking neural networks
The massively parallel nature of biological information processing plays an
important role for its superiority to human-engineered computing devices. In
particular, it may hold the key to overcoming the von Neumann bottleneck that
limits contemporary computer architectures. Physical-model neuromorphic devices
seek to replicate not only this inherent parallelism, but also aspects of its
microscopic dynamics in analog circuits emulating neurons and synapses.
However, these machines require network models that are not only adept at
solving particular tasks, but that can also cope with the inherent
imperfections of analog substrates. We present a spiking network model that
performs Bayesian inference through sampling on the BrainScaleS neuromorphic
platform, where we use it for generative and discriminative computations on
visual data. By illustrating its functionality on this platform, we implicitly
demonstrate its robustness to various substrate-specific distortive effects, as
well as its accelerated capability for computation. These results showcase the
advantages of brain-inspired physical computation and provide important
building blocks for large-scale neuromorphic applications.Comment: This preprint has been published 2019 November 14. Please cite as:
Kungl A. F. et al. (2019) Accelerated Physical Emulation of Bayesian
Inference in Spiking Neural Networks. Front. Neurosci. 13:1201. doi:
10.3389/fnins.2019.0120
The BrainScaleS-2 Neuromorphic Platform — A Report on the Integration and Operation of an Open Science Hardware Platform within EBRAINS
This report presents the challenges encountered and the solutions created for the operation of the BrainScaleS neuromorphic platform, and the overall progress leading to this state at the end of the Human Brain Project (HBP)
A Scalable Approach to Modeling on Accelerated Neuromorphic Hardware.
Neuromorphic systems open up opportunities to enlarge the explorative space for computational research. However, it is often challenging to unite efficiency and usability. This work presents the software aspects of this endeavor for the BrainScaleS-2 system, a hybrid accelerated neuromorphic hardware architecture based on physical modeling. We introduce key aspects of the BrainScaleS-2 Operating System: experiment workflow, API layering, software design, and platform operation. We present use cases to discuss and derive requirements for the software and showcase the implementation. The focus lies on novel system and software features such as multi-compartmental neurons, fast re-configuration for hardware-in-the-loop training, applications for the embedded processors, the non-spiking operation mode, interactive platform access, and sustainable hardware/software co-development. Finally, we discuss further developments in terms of hardware scale-up, system usability, and efficiency
From clean room to machine room: commissioning of the first-generation BrainScaleS wafer-scale neuromorphic system
The first-generation of BrainScaleS, also referred to as BrainScaleS-1, is a neuromorphic system for emulating large-scale networks of spiking neurons. Following a ‘physical modeling’ principle, its VLSI circuits are designed to emulate the dynamics of biological examples: analog circuits implement neurons and synapses with time constants that arise from their electronic components’ intrinsic properties. It operates in continuous time, with dynamics typically matching an acceleration factor of 10 000 compared to the biological regime. A fault-tolerant design allows it to achieve wafer-scale integration despite unavoidable analog variability and component failures. In this paper, we present the commissioning process of a BrainScaleS-1 wafer module, providing a short description of the system’s physical components, illustrating the steps taken during its assembly and the measures taken to operate it. Furthermore, we reflect on the system’s development process and the lessons learned to conclude with a demonstration of its functionality by emulating a wafer-scale synchronous firing chain, the largest spiking network emulation ran with analog components and individual synapses to date